The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a plurality of semiconductor integrated circuit chips mounted on a large-sized integrated circuit chip and capable of attaining high-density packaging with high yield, and to a computer system using the semiconductor integrated circuit device.
A packaging technique in a large-scale general-purpose computer or the like involves, for example, as described in the paper "PROCESSING SYSTEM AND HARDWARE TECHNIQUE OF LARGE SCALE COMPUTER M-880" Nikkei Electronics, Dec. 10, 1990 (No. 515), pp. 209-241, a technique in which a plurality of LSI chips are mounted on a ceramic wiring substrate (module) in face down fashion and the LSI chips are connected to one another or to external circuit devices outside of the module through solder bumps and the ceramic wiring substrate (this packaging technique is hereinafter referred to as a module packaging technique in the specification).
In tile module packaging technique, transmission of signals between the LSI chips on the ceramic wiring substrate is made by matched impedance transmission using terminating resistors in order to prevent the signals from being reflected at the of wiring ends. The terminating resistors are required in each wiring. The terminating resistors dissipate electric power regardless of the signal transmission and hence substantially large electric power is dissipated by the terminating resistors in the whole module.
Further, the pitch of terminals in the module cannot be made too small because of the strength of connection between the ceramic substrate and the terminals. Accordingly, there is an increased pin problem in that the number of terminals cannot be secured sufficiently as the scale or the number of circuits mountable on one module is increased.
On the other hand, a method using wafer scale integration circuit (hereinafter referred to as WSI) is known in order to realize a large scale integrated circuit device as compared with the module packaging technique. The WSI is used to integrate a plurality of LSI chips on the same wafer and make wiring among the LSI chips on the same wafer, so that connection terminals are not required to thereby lighten the burden on the packaging, and high-density packaging can thus be expected as compared with the module packaging technique. However, the WSI has a problem that a defect occurring in the process stage necessarily exists with a certain probability (problem as to a so-called yield). Thus, even if circuits are integrated with high density on the WSI, the probability that the circuits are operated successfully is very low. Accordingly, it is necessary to avoid or remedy the defect occurring in the process stage. In this respect, a method has been studied in which redundant logic circuits are provided previously in the design process and a portion in which a defect has been found is replaced by a separate normal logic circuit (so-called monolithic type wafer scale integration circuit).
Further, Japanese Patent Unexamined Publication No. 2-181465 discloses a method in which a plurality of chips which are confirmed to be operated successfully by previously implemented inspection are fixedly mounted vertically on a wafer to improve the yield as a system of combined wafer and chips (so-called hybrid type wafer scale integration circuit). This method can advantageously make a wiring pitch very much narrower as compared with the mounting of chips on the substrate and improve the packaging density.
However, wiring formed to connect among the chips on the wafer in the WSI is relatively long in distance, and thus wiring resistance is increased. In general, the propagation delay time of a signal propagated on the wiring formed on the integrated circuit chip is determined by a product of the wiring resistance and the wiring capacitance. Accordingly, as the wiring resistance is increased, the propagation delay time is also increased.
Additionally, Japanese Patent Unexamined Publication No. 3-69150 discloses a mounting structure for LSI chips in which a first LSI chip is mounted by second LSI chips smaller than the first LSI chip and both of them are connected to each other. In this method, the wiring distance between the first LSI chip and the second LSI chips can be made short and signals can be propagated at high speed. However, when the number of LSI chips is further increased, it is difficult to propagate signals among the LSI chips at high speed.